Compound semiconductor device with delta doped layer under etching stopper layer for decreasing resistance between active layer and ohmic electrode and process of fabrication thereof

ABSTRACT

A high electron mobility transistor has a channel layer overlain by an electron supply layer held in contact with a gate electrode, and source/drain electrodes form ohmic contact together with cap layers, and resistive etching stopper are inserted between the cap layers and the electron supply layers for preventing the electron supply layer from over-etching, wherein extremely thin delta-doped layers are formed between the etching stopper layers and the electron supply layer so that the resistance between the electron supply layer and the source/drain electrodes are reduced.

FIELD OF THE INVENTION

[0001] This invention relates to a compound semiconductor and, moreparticularly, to a compound semiconductor device having an etchingstopper layer between an active layer and an ohmic electrode.

DESCRIPTION OF THE RELATED ART

[0002] A heterojunction metal-semiconductor field effect transistor is atypical example of the compound semiconductor device. The high electronmobility transistor is a kind of heterojunction metal- semiconductorfield effect transistor, and is featured by an inversion layer at theboundary between an electron supply layer and a channel layer. Theheterojunction metal-semiconductor field effect transistor finds a widevariety of application such as, for example, a DBS (Direct BroadcastingSatellite). The compound semiconductor device is expected to have low-noise characteristics and achieve a high-gain.

[0003] In order to enhance the mutual conductance, it is known toincrease the dopant impurity in the electron supply layer. Reduction ofsource resistance is also appropriate. However, when the dopantconcentration is uniformly increased in the electron supply layer, aproblem is encountered in the heterojunction metal-semiconductor fieldeffect transistor in low withstand voltage between the gate electrodeand the electron supply layer.

[0004] A stepped doping concentration structure has been proposed. Whenthe stepped dopant concentration structure is applied to the electronsupply layer, the electron supply layer has a relatively heavy dopantconcentration close to the channel layer and a relatively light dopantconcentration close to the gate electrode.

[0005]FIG. 1 illustrates the prior art high electron mobility transistorwith the stepped dopant concentration structure. The prior art highelectron mobility transistor is fabricated on a semi-insulatingsubstrate 1, which is formed of gallium arsenide. The prior art highelectron mobility transistor comprises a buffer layer 2, a channel layer3, an electron supply layer 4/5, cap layers 8, ohmic electrodes 9 and agate electrode 10. Gallium arsenide is epitaxially grown on thesemi-insulating substrate 1, and forms a gallium arsenide layer. Thegallium arsenide layer serves as the buffer layer 2. On the galliumarsenide layer is epitaxially grown indium gallium arsenide which formsan indium gallium arsenide layer serving as the channel layer 3.Heavily-doped n-type aluminum gallium arsenide, i.e.,n⁺Al_(0.2)Ga_(0.8)As and lightly-doped n-type aluminum gallium arsenide,i.e., n⁻Al_(0.2)Ga_(0.8)As are successively epitaxially grown to 10nanometers thick and 20 nanometers thick on the indium gallium arsenidelayer, and form a heavily-doped n-type aluminum gallium arsenide layer 4and a lightly doped n-type aluminum gallium arsenide layer 5. The dopantconcentration is 4×10 ¹⁸/cm³ (4&times; 10⁻¹⁸/cm³) in the heavily-dopedn-type aluminum gallium arsenide layer 4 and 1×10¹⁷/cm³ in thelightly-doped n-type aluminum gallium arsenide layer 5. Theheavily-doped n-type aluminum gallium arsenide layer 4 and thelightly-doped n-type aluminum gallium arsenide layer 5 form incombination the electron supply layer 4/5. The heavily-doped n-typealuminum gallium arsenide layer 4 is contiguous to the channel layer 3,and the gate electrode 10 is held in contact with the lightly-dopedn-type aluminum gallium arsenide layer 5. The n-type dopantconcentration is changed at the boundary between the heavily-dopedn-type aluminum gallium arsenide layer 4 and the lightly-doped n-typealuminum gallium arsenide layer 5. Thus, the electron supply layer 4/5has the stepped dopant concentration structure.

[0006] On the lightly-doped aluminum gallium arsenide layer 5 isepitaxially grown heavily-doped n-type gallium arsenide from which formsthe cap layers 8 of 80 nanometers thick are formed. The dopantconcentration is 3×10¹⁸/cm³ in the heavily-doped n-type gallium arsenidelayer. Namely, the heavily-doped n-type gallium arsenide layer ispartially etched so as to expose the electron supply layer 4/5 to arecess between the cap layers 8. The gate electrode 10 is held incontact with the exposed portion of the electron supply layer 5. On theother hand, the ohmic electrodes 9 are held in contact with the caplayers on both sides of the recess, and serve as a source electrode anda drain electrode.

[0007] The prior art high electron mobility transistor achieves a largemutual conductance by virtue of the heavily-doped n-type aluminumgallium arsenide layer 4 as well as a high withstand voltage by virtueof the lightly-doped n-type aluminum gallium arsenide layer 5. However,the threshold voltage and, accordingly, the amount of channel currentare liable to fluctuate among the products. This is because of the factthat the etchant is liable to partially remove the lightly-doped n-typealuminum gallium arsenide layer 5 during the formation of the recess.

[0008] An etching stopper has been proposed as a countermeasure againstthe problem. The recess is formed by using mixture of citric acid andH₂O₂ as wet etchant. Upon completion of the fabrication process, theprior art high electron mobility transistor has the structure shown inFIG. 2.

[0009] The prior art high electron mobility transistor is fabricated ona semi-insulating substrate 1, which is formed of gallium arsenide. Theprior art high electron mobility transistor comprises a buffer layer 2,a channel layer 3, an electron supply layer 4/5, etching stopper layers7, cap layers 8, ohmic electrodes 9 and a gate electrode 10. Galliumarsenide is epitaxially grown on the semi-insulating substrate 1, andforms a gallium arsenide layer. The gallium arsenide layer serves as thebuffer layer 2. On the gallium arsenide layer is epitaxially grownindium gallium arsenide which forms an indium gallium arsenide layerserving as the channel layer 3. Heavily-doped n-type aluminum galliumarsenide, i.e., n⁺Al_(0.2)Ga₀ ₈As and lightly-doped n-type aluminumgallium arsenide, i.e., n⁻Al_(0.2)Ga_(0.8)As are successivelyepitaxially grown to 10 nanometers thick and 20 nanometers thick on theindium gallium arsenide layer, and form a heavily-doped n-type aluminumgallium arsenide layer 4 and a lightly-doped n-type aluminum galliumarsenide layer 5. The dopant concentration is 4×10¹⁸/cm³ in theheavily-doped n-type aluminum gallium arsenide layer 4 and 1×10¹⁷/cm³ inthe lightly-doped n-type aluminum gallium arsenide layer 5. Theheavily-doped n-type aluminum gallium arsenide layer 4 and thelightly-doped n- type aluminum gallium arsenide layer 5 form incombination the electron supply layer 4/5. The heavily-doped n-typealuminum gallium arsenide layer 4 is contiguous to the channel layer 3,and the gate electrode 10 is held in contact with the lightly-dopedn-type aluminum gallium arsenide layer 5. The n-type dopantconcentration is changed at the boundary between the heavily-dopedn-type aluminum gallium arsenide layer 4 and the lightly-doped n-typealuminum gallium arsenide layer 5. Thus, the electron supply layer 4/5has the stepped dopant concentration structure.

[0010] On the lightly-doped aluminum gallium arsenide layer 5 is grownlightly-doped n-type aluminum gallium arsenide n⁻Al_(0.7)Ga_(0.3)Aswhich forms a lightly-doped n-type aluminum gallium arsenide layer. Theetching stopper layers 7 are formed from the lightly-doped n-typealuminum gallium arsenide layer. Heavily-doped n-type gallium arsenideis epitaxially grown to 80 nanometers thick on the lightly-doped n-typealuminum gallium arsenide layer 7, and forms a heavily-doped n-typegallium arsenide layer. The cap layers 8 are formed from theheavily-doped n-type gallium arsenide layer. The dopant concentration is3×10¹⁸/cm³ in the heavily-doped n-type gallium arsenide layer. Theheavily-doped n-type gallium arsenide layer 8 and the lightly-dopedaluminum gallium arsenide layer 7 are partially etched so as to exposethe electron supply layer 4/5 to a recess between the cap layers 8. Thegate electrode 10 is held in contact with the exposed portion of theelectron supply layer 5. On the other hand, the ohmic electrodes 9 areheld in contact with the cap layers on both sides of the recess, andserve as a source electrode and a drain electrode.

[0011] The lightly-doped n-type Al_(0.7)Ga_(0.3)As layer 7 gives an endpoint to the wet etchant in the formation of the recess, and preventsthe lightly doped Al_(0.8)Ga₀ ₂As layer 5 from the wet etchant. As aresult, the electron supply layer 4/5 is constant in thickness, and theelectron supply layer 4/5 keeps the threshold constant among products.

[0012] However, a problem is encountered in the prior art high electronmobility transistor shown in FIG. 2 in the high source resistance.

SUMMARY OF THE INVENTION

[0013] It is therefore an important object of the present invention toprovide a compound semiconductor device, which is reduced in sourceresistance without sacrifice of the constant thickness of the activelayer.

[0014] It is also an important object of the present invention toprovide a process for fabricating the compound semiconductor device.

[0015] The present inventors contemplated the problem inherent in theprior art high electron mobility transistor shown in FIG. 2, and noticedthat the n⁻Al_(0.7)Ga_(0.3)As etching stopper layers 7 were left betweenthe electron supply layer 5 and the cap layers 8. Aluminum had the largecomposition ratio in the n⁻Al_(0.7)Ga_(0.3)As. The aluminum was a largeamount of dx center, and the dx centers were not activated with then-type dopant impurity, i.e., silicon. Even though the silicon was dopedin the Al_(0.7)Ga_(0.3)As, a non-ignoreable amount of n-type dopantimpurities were invalid, and the lightly-doped Al_(0.7)Ga_(0.3)As layerexhibited high resistivity. The present inventors replaced thelightly-doped n⁻Al_(0.7)Ga_(0.3)As etching stopper layers 7 withnon-doped etching stopper layers. The high electron mobility transistoralso exhibited large source resistance. The present inventors concludedthat the resistance was to be reduced without deleting the etchingstopper layer was required.

[0016] To accomplish the object, the present invention proposes toreduce the potential barrier between cap layers and an active layer byusing delta-doped layers.

[0017] In accordance with one aspect of the present invention, there isprovided a compound semiconductor device fabricated on a substratecomprising a multiple-layered structure including an active layer,plural cap layers respectively located over plural portions of theactive layer, plural highly-resistive layers formed between themultiple-layered structure and the plural cap layers so as to form arecess located over a part of the multiple- layered structure andbetween the plural cap layers, plural delta-doped layers formed betweenthe plural highly-resistive layers and the multiple- layered structurefor decreasing potential barriers of the plural highly-resistive layers,a first electrode held in contact with the part of the multiple- layeredstructure for controlling the amount of current flowing through theactive layer, and second electrodes respectively formed on the pluralcap layers for providing current paths from and to the active layerthrough the plural cap layers, the plural highly-resistive layers andthe plural delta-doped layers.

[0018] In accordance with another aspect of the present invention, thereis provided a process for fabricating a compound semiconductor devicecomprising the steps of a) producing a multiple-layered structure havingan active layer, a delta-doped layer over the active layer, a highlyresistive layer over the delta-doped layer and a highly conductive layerover the delta-doped layer on a semi-insulating substrate, b) removing apart of the highly conductive layer so as to expose a part of the highlyresistive layer to a first opening formed between remaining portions ofthe highly conductive layer serving as plural cap layers, c) removingthe part of the highly resistive layer and a part of the delta-dopedlayer thereunder so as to expose a part of the active layer to a secondopening formed between plural delta doped layers respectively overlainby highly resistive layers and d) completing a compound semiconductordevice having a first electrode held in contact with the part of theactive layer and second electrodes respectively held in contact with theplural cap layers.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The features and advantages of the compound semiconductor deviceand the fabrication process will be more clearly understood from thefollowing description taken in conjunction with the accompanyingdrawings in which:

[0020]FIG. 1 is a cross sectional view showing the prior art highelectron mobility transistor with the stepped dopant concentrationstructure;

[0021]FIG. 2 is a cross sectional view showing the prior art highelectron mobility transistor with the etching stopper between theelectron supply layer and the cap layers;

[0022]FIG. 3 is a cross sectional view showing the structure of a highelectron mobility transistor according to the present invention;

[0023] FIGS. 4 is an energy band diagram showing the energy band createdin the high electron mobility transistor;

[0024]FIGS. 5A to 5C are cross sectional views showing a process forfabricating the high electron mobility transistor according to thepresent invention;

[0025]FIG. 6 is a cross sectional view showing the structure of aheterojunction metal-semiconductor field effect transistor according tothe present invention; and

[0026]FIGS. 7A to 7D are cross sectional views showing a process forfabricating the heterojunction metal-semiconductor field effecttransistor according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] First Embodiment

[0028] Referring to FIG. 3 of the drawings, a high electron mobilitytransistor embodying the present invention is fabricated on a semi-insulating substrate 1 of gallium arsenide. The high electron mobilitytransistor comprises a buffer layer 2, a channel layer 3, an electronsupply layer 4/5, delta doped layers 6, etching stopper layers 7, caplayers 8, ohmic electrodes 9 and a gate electrode 10. The delta dopedlayers are referred to as “planar dope layer” or “pulse dope layer” inseveral articles. In other words, the term “delta doped layer” issynonymous with the term “planar dope layer” and the term “pulse dopelayer”. The delta doped layers 6 are hereinlater described in detail.

[0029] The buffer layer 2 is formed of gallium arsenide epitaxiallygrown on the semi-insulating substrate 1 of gallium arsenide. Thechannel layer 3 is formed of indium gallium arsenide epitaxially grownon the gallium arsenide buffer layer 2. The electron supply layer 4/5has the stepped dopant concentration structure, and the stepped dopantconcentration structure is implemented by a heavily-doped n-typealuminum gallium arsenide layer 4 and a lightly-doped n-type aluminumgallium arsenide layer 5. The heavily-doped n- type aluminum galliumarsenide and the lightly-doped n-type aluminum gallium arsenide have thecomposition expressed as Al_(0.2)Ga_(0.8)As. The heavily-doped n-typealuminum gallium arsenide layer 4 is 10 nanometers thick, and the dopantconcentration is 4×10¹⁸/cm³ in the heavily-doped n-type aluminum galliumarsenide layer 4. On the other hand, the lightly-doped n-type aluminumgallium arsenide layer 5 is 20 nanometers thick, and the dopantconcentration is 1×10¹⁷/cm³ in the lightly-doped n-type aluminum galliumarsenide layer 5.

[0030] The delta doped layers 6 are formed by supplying Group-V element,i.e., arsenic (As) and silicon, only, and are as thin as a single atomto several atoms. The silicon is delta doped. For this reason, thedopant impurity, i.e., silicon is heavily contained in the delta dopedlayer 6. The dopant impurity concentration of the delta-doped layers 6are heavier than that of the electron supply layer. In this instance,the delta doped layers 6 contain the silicon at 6×10¹²/cm². The deltadoped layers 6 contain only one kind of dopant impurity so that thetunneling phenomenon takes place at the boundaries. For this reason, thecarriers can pass a potential barrier larger in height than the energythereof.

[0031] The etching stopper layers 7 are formed of lightly-doped aluminumgallium arsenide epitaxially grown on the delta doped layers 6. Thelightly-doped aluminum gallium arsenide is different in composition fromthat of the electron supply layer 4/5, and is expressed asAl_(0.7)Ga_(0.3)As. Although silicon is lightly doped into the aluminumgallium arsenide Al_(0.7)Ga_(0.3)As, the aluminum gallium arsenideAl_(0.7)Ga_(0.3)As contains a large amount of dx centers, and the dxcenters deactivate the silicon. For this reason, the effective carrierdensity is drastically decreased in the aluminum gallium arsenideetching stopper layers 7.

[0032] The cap layers 8 are formed from a heavily-doped n-type galliumarsenide layer epitaxially grown on the aluminum gallium arsenideetching stopper layers 7. The cap layers 8 are 80 nanometers thick, andthe dopant concentration is 3×10¹⁸/cm³.

[0033] The heavily-doped n-type gallium arsenide layer 8, thelightly-doped aluminum gallium arsenide layer 7 and the delta dopedlayer 6 are partially etched away so that the electron supply layer 5 isexposed to a recess between the cap layers 8. The ohmic electrodes 9 areheld in contact with the cap layers 8, and the gate electrode 10 is heldin contact with the lightly-doped aluminum gallium arsenide layer 5 ofthe electron supply layer.

[0034] The energy band shown in FIG. 4 is created in the high electronmobility transistor according to the present invention. If the deltadoped layers 6 are not inserted between the electron supply layer 4/5and the etching stopper layers, the bottom edge of conduction band isrepresented by broken line. The potential barriers between the caplayers 8 and the etching stopper layers 7 and between the etchingstopper layers 7 and the electron supply layer 5 are wide. The deltadoped layers 6 make the potential level of the etching stopper layers 7lower. The potential barriers between the cap layers 8 and the etchingstopper layers 7 and between the etching stopper layers 7 and theelectron supply layer 5 are made narrow. As a result, the carriers orelectrons are smoothly moved between the ohmic electrodes 9 and thechannel layer 3, and, accordingly, the resistance is decreased.

[0035] The etching stopper 7 keeps the electron supply layer 4/5constant in thickness among the products. The electron supply layer 4/5with constant thickness is effective against the fluctuation ofthreshold voltage. Thus, the high electron mobility transistor accordingto the present invention achieves the low resistance without sacrificeof the constant thickness of the electron supply layer 4/5.

[0036] The high electron mobility transistor shown in FIG. 3 isfabricated through a process shown in FIGS. 5A to 5C. In the followingdescription, compound semiconductor layers are labeled with thereferences designating the layers of the high electron mobilitytransistor shown in FIG. 3.

[0037] The process starts with preparation of the semi- insulatingsubstrate 1. The gallium arsenide layer 2, the indium gallium arsenidelayer 3, the heavily-doped aluminum gallium arsenide layer 4, thelightly-doped aluminum gallium arsenide layer 5, the delta doped layers6, the aluminum gallium arsenide layer 7 and the heavily-doped galliumarsenide layer 8 are epitaxially grown on the semi-insulating substrate1 in succession. Nickel-gold-germanium alloy Ni/AuGe is grown on theheavily-doped gallium arsenide layer 8, and the ohmic electrodes 9 areformed from the nickel-gold- germanium alloy layer. The resultantsemiconductor structure in this stage is shown in FIG. 5A.

[0038] Subsequently, a photo-resist mask 11 is provided on the resultantsemiconductor structure by using a photo- lithography. Namely,photo-resist solution is spread over the resultant semiconductorstructure, and is baked so as to form a photo-resist layer. A patternimage is transferred from a photo-mask to the photo-resist layer so asto produce a latent image in the photoresist layer. The latent image isdeveloped. Then, the photo-resist mask 11 is left on the resultantsemiconductor structure. A part of the heavily-doped gallium arsenidelayer 8 is exposed to the opening formed in the photo-resist mask 11.Using wet etchant containing citric acid and hydrogen peroxide H₂O₂, theheavily-doped gallium arsenide layer 8 is partially removed. Since thewet etchant has the selectivity larger to the gallium arsenide than tothe lightly-doped n-type aluminum gallium arsenide Al_(0.7)Ga_(0.3)As,the wet etching is terminated on the lightly-doped n- type aluminumgallium arsenide Al_(0.7)Ga_(0.3)As layer 7, and a recess 12 is formedin the heavily-doped n-type gallium arsenide layer 8 as shown in FIG.5B. Thus, the lightly-doped n-type aluminum gallium arsenideAl_(0.7)Ga_(0.3)As layer 7 serves as an etching stopper. While thelightly.-doped n- type aluminum gallium arsenide Al_(0.7)Ga_(0.3)Aslayer 7 is being etched with the wet etchant, the exposed portion of thelightly-doped n-type aluminum gallium arsenide Al_(0.7)Ga_(0.3)Asetching stopper layer 7 is oxidized, and aluminum oxide Al₂O₃ is left onthe delta-doped layers 6.

[0039] As described hereinbefore, the lightly-doped n- type aluminumgallium arsenide Al_(0.7)Ga_(0.3)As layer 7 contains a large amount ofdx centers. For this reason, the dopant impurity, i.e., silicon atomsare hardly activated, and the actual carrier concentration isdrastically reduced. This means that the lightly-doped n-type aluminumgallium arsenide Al_(0.7)Ga_(0.3)As layer 7 is highly resistive.

[0040] The aluminum oxide layer and the delta-doped layers 6 under thealuminum oxide layer are etched away by using hydrochloric acid. Thelightly-doped n-type aluminum gallium arsenide layer 5 is hardly etchedso that the high electron mobility transistor is constant in thresholdand the amount of channel current among products. Finally, titanium-aluminum alloy is deposited over the entire surface by using anevaporation technique, and the photo-resist mask 11 is stripped offtogether with the titanium-aluminum alloy deposited thereover. The gateelectrode 10 is left on the electron supply layer 4/5 as shown in FIG.5C.

[0041] As will be understood from the foregoing description, thepotential barrier of the etching stopper layer 7 is lowered by virtue ofthe delta-doped layers 6, and the resistance between the ohmicelectrodes 9 and the electron supply layer 4/5 is decreased. As aresult, the source resistance of the high electron mobility transistoris reduced, and the high-frequency characteristics such as, for example,the noise factor and the gain are improved.

[0042] The delta-doped layers are removed from the upper surface of theelectron supply layer 4/5 exposed to the recess 12. This means that thegate electrode 10 is directly held in contact with the electron supplylayer 4/5. This results in a small amount of gate leakage current and ahigh gate-and-drain withstand voltage.

[0043] In the first embodiment, the channel layer 3 and the electronsupply layer 4/5 as a whole constitute an active layer.

[0044] Second Embodiment

[0045]FIG. 6 illustrates another high electron mobility transistorembodying the present invention. The high electron mobility transistoris fabricated on a semi- insulating substrate 1 of gallium arsenide. Thehigh electron mobility transistor comprises a buffer layer 2, a channellayer 3, an electron supply layer 4 a, delta doped layers 6, undopedgallium arsenide layer 7 a, cap layers 8, ohmic electrodes 9, a gateelectrode 10 and a protective layer 14.

[0046] The buffer layer 2 is formed of gallium arsenide epitaxiallygrown on the semi-insulating substrate 1 of gallium arsenide. Thechannel layer 3 is formed of indium gallium arsenide epitaxially grownon the gallium arsenide buffer layer 2. The electron supply layer 4 a isformed of n-type gallium arsenide, and the dopant concentration is1×10¹⁸/cm³ in the n-type gallium arsenide electron supply layer 4 a. Then-type gallium arsenide electron supply layer 4 a is 30 nanometersthick.

[0047] The delta doped layers 6 are similar to those of the firstembodiment, and no further description is incorporated hereinbelow foravoiding repetition. The undoped gallium arsenide layers 7 a are 20nanometers thick. An etching stopper layer may be inserted between thecap layers 8 and the undoped gallium arsenide layers 7 a.

[0048] The cap layers 8 are formed from a heavily-doped n-type galliumarsenide layer epitaxially grown on the undoped gallium arsenide layers7 a. The cap layers 8 are 80 nanometers thick, and the dopantconcentration is 3×10¹⁸/cm³.

[0049] The heavily-doped n-type gallium arsenide layer 8, the undopedgallium arsenide layer 7 a and the delta doped layer 6 are partiallyremoved, and a part of the n-type gallium arsenide layer 4 a is exposedto a recess between the undoped gallium arsenide layers 7 a. The ohmicelectrodes 9 are held in contact with the cap layers 8, and the gateelectrode 10 is held in contact with the n-type gallium arsenideelectron supply layer 4 a. The protective layer 14 is formed of silicondioxide, and fills an upper portion of the recess.

[0050] The high electron mobility transistor is fabricated as follows.The process starts with preparation of the semi-insulating substrate 1.The gallium arsenide layer 2, the indium gallium arsenide layer 3, then-type gallium arsenide layer 4 a, the delta doped layer 6, the undopedgallium arsenide layer 7 a and the heavily-doped n-type gallium arsenidelayer 8 are enitaxially grown on the major surface of thesemi-insulating substrate 1.

[0051] A photo-resist etching mask 11 a is formed on the heavily-dopedn-type gallium arsenide layer 8 through the photo-lithographictechniques. Using the photo-resist etching mask 11 a, the heavily-dopedn- type gallium arsenide layer 8 is partially etched away, and a widerecess 12 a takes place in the heavily-doped n- type gallium arsenidelayer 8. The remaining portions of the heavily-doped n-type galliumarsenide layer 8 serve as the cap layers 8. The resultant semiconductorstructure is shown in FIG. 7A. In the case where the etching stopperlayer of aluminum gallium arsenide layer is inserted between the undopedgallium arsenide layer 7 a and the heavily-doped n-type gallium arsenidelayer 8, the etching is exactly terminated at the etching stopper layer.

[0052] Silicon dioxide is deposited over the entire surface of theresultant semiconductor structure by using a chemical vapor deposition.The silicon dioxide forms a silicon dioxide layer 14. A photo-resistetching mask (not shown) is formed on the silicon dioxide layer 14, andhas an opening over the n-type gallium arsenide layer where the gateelectrode 10 is to be formed. Using the photo-resist etching mask, thesilicon dioxide layer is partially etched away, and a gate opening 15 isformed in the silicon dioxide layer 14 as shown in FIG. 7B.

[0053] Subsequently, the undoped gallium arsenide layer 7 a and thedelta-doped layer 6 are partially etched away by using the photo-resistetching mask. This results in a gate recess 12 b, and the part of then-type gallium arsenide electron supply layer 4 a is exposed to the gaterecess 12 b as shown in FIG. 7C.

[0054] WSi—TiN—Pt—Au alloy is deposited over the entire surface of theresultant semiconductor structure by using a sputtering technique, andthe alloy is patterned into the gate electrode 10 by using the photo-lithographic techniques followed by an etching. Finally, the ohmicelectrodes 9 of Ni—AuGe alloy is formed on the cap layers 8, and thehigh electron mobility transistor is obtained as shown in FIG. 7D.

[0055] As similar to the high electron mobility transistor implementingthe first embodiment, the delta-doped layers 6 lower the potentialbarriers of the undoped gallium arsenide layers 7 a, and decrease theresistance between the channel layer 3 and the ohmic electrodes 9. Eventhough the delta-doped layers 6 are inserted between the undoped galliumarsenide layers 7 a and the n-type gallium arsenide electron supplylayer 4 a, the gate electrode 10 is directly held in contact with then-type gallium arsenide electron supply layer 4 a. For this reason, theleakage current is not increased, and the gate-and-drain withstandvoltage (BVgd) is not lowered.

[0056] Although particular embodiments of the present invention havebeen shown and described, it will be apparent to those skilled in theart that various changes and modifications may be made without departingfrom the spirit and scope of the present invention.

[0057] In the first embodiment, the etching stopper layers 7 are formedof Al_(0.7)Ga_(0.3)As. The composition ratio of aluminum is allowed tobe different from 0.7 in so far as the aluminum gallium arsenide givesthe end point to the etchant.

[0058] A dry etching technique is available for the step for patterningthe heavily-doped n-type gallium arsenide layer 8. The heavily-dopedn-type gallium arsenide layer 8 may be patterned by using another kindof etchant such as, for example, gaseous mixture of BCl₃ and SF₆ oranother kind of gaseous mixture of SiCl₄ and SF₆.

[0059] The metal-semiconductor field effect transistor implementing thefirst embodiment may not be equipped with any electron supply layer. Thestandard metal-semiconductor field effect transistor may have thestructure comprising a gallium arsenide buffer layer 2, ann⁺Al_(0.2)Ga_(0.8)As /n⁻Al_(0.2)Ga_(0.8)As channel layer 4/5, deltadoped layers 6, n⁻Al_(0.7)Ga_(0.3)As etching stopper layers 7 and n⁺GaAscap layers 8. The standard metal- semiconductor field effect transistormay be categorized in the metal-semiconductor Schottky field effecttransistor. The metal-semiconductor Schottky field effect transistor maycomprise a gallium arsenide buffer layer 2, an n⁺Al_(0.2)Ga_(0.8)As/n⁻Al_(0.2)Ga₀ ₈As channel layer 4/5, delta doped layers 6,n⁻Al_(0.7)Ga_(0.3)As etching stopper layers 7 and n⁺GaAs cap layers 8.

[0060] The undoped gallium arsenide layer 7 a may be replaced withanother kind of undoped compound semiconductor layer such as, forexample, undoped aluminum gallium arsenide layer or undoped indiumgallium arsenide layer.

What is claimed is:
 1. A compound semiconductor device fabricated on asubstrate, comprising: a multiple-layered structure including an activelayer; plural cap layers respectively located over plural portions ofsaid active layer; plural highly-resistive layers formed between saidmultiple-layered structure and said plural cap layers so as to form arecess located over a part of said multiple-layered structure andbetween said plural cap layers; plural delta-doped layers formed betweensaid plural highly-resistive layers and said multiple-layered structurefor decreasing potential barriers of said plural highly-resistivelayers; a first electrode held in contact with said part of saidmultiple-layered structure for controlling the amount of current flowingthrough said active layer; and second electrodes respectively formed onsaid plural cap layers for providing current paths from and to saidactive layer through said plural cap layers, said pluralhighly-resistive layers and said plural delta-doped layers.
 2. Thecompound semiconductor device as set forth in claim 1, in which saidplural delta-doped layers are thin so that a tunneling phenomenon takesplace.
 3. The compound semiconductor device as set forth in claim 1, inwhich the thickness of said plural delta-doped layers is equal to asingle atom to several atoms.
 4. The compound semiconductor device asset forth in claim 1, in which said plural delta doped layers containonly one kind of dopant impurity.
 5. The compound semiconductor deviceas set forth in claim 1, in which said active layer has a conductivechannel layer for said current.
 6. The compound semiconductor device asset forth in claim 5, in which said active layer further has a carriersupply layer for producing an inversion layer at the boundary betweensaid carrier supply layer and said conductive channel layer.
 7. Thecompound semiconductor device as set forth in claim 6, in which saidcarrier supply layer has a large dopant concentration in a first portionclose to the boundary formed with said channel layer and a small dopantconcentration in a second portion close to said gate electrode.
 8. Thecompound semiconductor device as set forth in claim 1, in which saidplural highly-resistive layers serve as an etching stopper forpreventing said active layer from an etchant used for patterning saidplural cap layers.
 9. The compound semiconductor device as set forth inclaim 1, in which said plural highly-resistive layers are formed ofundoped compound semiconductor.
 10. A process for fabricating a compoundsemiconductor device, comprising the steps of: a) producing amultiple-layered structure having an active layer, a delta-doped layerover said active layer, a highly resistive layer over said delta-dopedlayer and a highly conductive layer over said delta-doped layer on asemi-insulating substrate; b) removing a part of said highly conductivelayer so as to expose a part of said highly resistive layer to a firstopening formed between remaining portions of said highly conductivelayer serving as plural can layers; c) removing said part of said highlyresistive layer and a part of said delta-doped layer thereunder so as toexpose a part of said active layer to a second opening formed betweenplural delta doped layers respectively overlain by highly resistivelayers; and d) completing a compound semiconductor device having a firstelectrode held in contact with said part of said active layer and secondelectrodes respectively held in contact with said plural cap layers. 11.The process as set forth in claim 10, in which said highly resistivelayer serves as an etching stopper carried out in said step b) so as toprevent said active layer from a first etchant.
 12. The process as setforth in claim 11, in which step b) includes the sub-steps of b-1)forming an etching mask on said highly conductive layer, and b-2)exposing said highly conductive layer to said first etchant having alarge selectivity to a first kind of compound semiconductor forming saidhighly conductive layer with respect to a second kind of compoundsemiconductor forming said highly resistive layer.
 13. The process asset forth in claim 12, in which said first etchant contains an oxidizingagent for producing an oxide from said second kind of compoundsemiconductor.
 14. The process as set forth in claim 13, in which asecond etchant is used for removing said oxide and said part of saiddelta-doped layer, and has a large selectivity to said oxide and saiddelta-doped layer with respect to a third kind of compound semiconductorforming said active layer.
 15. The process as set forth in claim 13, inwhich said oxidizing agent is hydrogen peroxide, and said first kind ofcompound semiconductor and said second kind of compound semiconductorcontain a negligible amount of aluminum and a large amount of aluminum,respectively.
 16. The process as set forth in claim 15, in which saidfirst etchant further contains citric acid, and said first kind ofcompound semiconductor and said second kind of compound semiconductorare gallium arsenide and aluminum gallium arsenide, respectively. 17.The process as set forth in claim 10, in which said step b) includes thesub-steps of b-1) depositing an oxide over said highly conductive layerfor forming an oxide layer, b-2) partially removing said oxide layer forforming an etching mask, and b-3) etching said part of said highlyconductive layer by using said etching mask.
 18. The process as setforth in claim 17, in which said etching mask serves as a protectivelayer surrounding said first electrode.